1. Field of the Invention
The present invention is directed to phase detectors and, more particularly, to phase locked and delay locked loops comprised of all digital components.
2. Description of the Background
A phase locked loop is a circuit designed to minimize the phase difference between two signals. When the phase difference approaches zero, or is within a specified tolerance, the phase of the two signals is said to be xe2x80x9clockedxe2x80x9d. A delay locked loop is similar to a phase locked loop, but instead of producing an output signal which has the same phase as an input or reference signal, the delay locked loop passes a reference or input signal into a delay line, and the output of the delay line has some predefined phase delay with respect to the reference or input signal.
Phase locked loops (PLL""s) and delay locked loops (DLL""s) are widely used circuits where it is necessary to have two signals which have a known relationship to one another. For example, when transmitting information from a sending device to a receiving device, it is necessary to have the local clock of the receiving device in sync with the clock of the sending device so that the information can be reliably transmitted. A PLL may be used for that purpose. Both PLL""s and DLL""s have been used for a long period of time, and numerous analog examples of these circuits can be found in the literature and in many devices.
A phase detector is a very important part of a PLL or DLL. The phase detector is used to provide phase discrimination and generate a control signal which is then used to speed up or slow down the local signal so that a desired relationship between the local signal and the reference signal is obtained.
FIG. 1 illustrates an analog prior art circuit used to produce a control signal Vc which is input to a voltage controlled oscillator (not shown) or voltage controlled delay line (not shown) to either advance or retard the phase of output signal Vo. The output signal Vo produced by the voltage controlled oscillator or voltage controlled delay line is then fed back to the phase detector 10. The phase detector also receives a reference signal Vref. The phase detector may be implemented by an edge-triggered D-type flipflop or an RS latch. Those devices generate an UP/DOWN signal having a pulse width that is proportional to the phase difference between the two signals. The UP/DOWN signal can then be used to control a charge pump circuit 12. The output of the charge pump circuit 12 is fed into a loop filter 13, which integrates and generates the analog voltage Vc used to control the voltage controlled oscillator or voltage controlled delay line.
FIG. 2 illustrates the relationship between the signals Vref, Vo and the UP/DOWN signal of FIG. 1. FIG. 2 illustrates the situation when the loop is close to xe2x80x9clock.xe2x80x9d Under those conditions, the pulse width of the UP and DOWN signals is narrow.
PLL""s and DLL""s are used in a variety of devices where the PLL or DLL can be constructed of all digital components. The all-digital approach has the benefits of being portable and scalable for other processes and applications. For example, all digital implementations of PLL""s and DLL""s are needed for such complex circuits as memory devices. The system clock of certain types of memory devices needs to be in sync with, for example, data so that data may be reliably written to or read from the memory. PLL""s and DLL""s are also needed when transferring data within the memory device to insure, for example, that data read out of the memory is properly presented to output pads.
A problem occurs when traditional phase detectors are used for all digital PLL""s and DLL""s. For all digital loops, there is no integration of the UP/DOWN signal as occurs in analog loops. As a result, mutually exclusive signals are needed to control all digital loops. More specifically, the UP signal and DOWN signal cannot occur at the same time. Furthermore, the control signals need to be well-defined digital pulses even when the loop is close to xe2x80x9clockxe2x80x9d to insure that the appropriate action is taken. Thus, the need exists for a phase detector suitable for use in all digital PLL""s and DLL""s which can reliably produce control signals even when the loop is close to locked conditions.
The present invention is directed to a phase detector comprised of two cross-coupled logic gates for providing phase discrimination between a clock, or reference, signal and a feedback, or output, signal. A plurality of transistors are responsive to the logic gate for generating mutually exclusive UP and DOWN signals. A filter receives the UP and DOWN signals and produces control signals therefrom.
The present invention also directed to a method of discriminating between a local or chip clock signal and a reference clock signal to produce first and second signals which do not have coincident leading edges. The first and second signals are then filtered to produce first and second control signals, respectively.
The present invention provides a novel phase detector using a two-way arbiter designed to discriminate a small phase error and provide all the features required by an all digital loop. The phase detector of the present invention can detect phase error down to 10 pico-seconds and produce UP and DOWN signals having a pulse width equal to one-half of the cycle of the clock signals, regardless of how close the loop is to xe2x80x9clock.xe2x80x9d An n-bit counter, shift register, or other device provides noise filtering to select certain of the UP/DOWN signals to generate FAST and SLOW control signals to control the loop. The phase detector of the present invention provides for fast locking and stable operation of the loop with low jitter. Those, and other advantages and benefits, will be apparent from the Description of the Preferred Embodiment appearing hereinbelow.